Synopsys is at the forefront of Smart Everything with the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. We help our customers innovate from silicon to software so they can bring amazing new products to life.

Synopsys hiring fresher R&D  Software Engineer with good programming capability C-Shell, Perl. C++ or Java script and proficient with CMOS memory design knowledge.

Job Designation : Software R&D Engineer

Salary : 6 LPA – 9 LPA

Qualification : Bachelor’s or Master’s degree

Experience : Freshers / 0-1 years

Skill Set :

1. Proficient with CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction.
2. Good knowledge of layout verification tools and debugging techniques.
3. Good programming capability C-Shell, Perl. C++ or Java script.
4. Can develop a document, report or presentation for a range of tasks .
5. Proficeint in Microsoft Office: Word, Excel, PowerPoint, Shared point and Outlook .
6. Excellent analytical and problem solving skills along with attention to details.
7. Self-motivated, self-directed, detailed oriented and well organized
8. Good analytical, problem solving and negotiation skills
9. Ability to lead/mentor trainees and junior engineers as well as lead and manage projects.
10. A strong command of English both verbal and written
11. Strong interpersonal communication and team working skills
12. Professionalism, Critical/Logical thinking, future goals focused
13. High commitment to continuous learning.

Job Description :

1. Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM:
2. Design architecture and circuit implementation, especially ultra high speed, ultra low power, or high density design portfolio.
3. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification and validation.
4. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation and full verification flow.
5. Perform bit cell development and bit cell verification, and drive physical layout design and verification.
6. Provide support and/or perform other duties as assigned and required.
7. Schedule own work flow .
8. Normally receives little instruction on day-to-day work, general instructions on new assignments.
9. Demonstrates good judgment in selecting methods and techniques for obtaining solutions.

Location : Noida, India