Chandu Srinadh About Me Work & Experience Design Verification Trianee(Intern) May 2, 2022 Excel VLSI Know developing Testbenches using UVM, System Verilog. Protocols known AMBA AXI AHB APB. Skills UVM Be the first to review “Chandu Srinadh” Cancel reply Your Rating for this listingYour Rating Name Email Save my name, email, and website in this browser for the next time I comment. Review Δ This site uses Akismet to reduce spam. Learn how your comment data is processed.
