Synopsys re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.

Synopsys  hiring a highly motivated fresher innovative digital verification engineer with excellent theoretical and practical background in high-speed data recovery circuits.

Job Designation : Technical Engineering intern

Qualification : Bachelor’s or Master’s degree

Experience : Freshers

Skill Set :

1. Expertise in writing scripts in languages such as Perl, Python, Unix shell.
2. Strong knowledge in Processor architecture and ASIC Design flow,HDL Verilog/VHDL/SV,
3. Good knowledge of design patterns and practical application of same.
4. Familiar with Verification and Synthesis basics,
5. Strong abstraction, analytical and problem-solving skills.
6. Good debug and problem-solving skills.
7. Good communication skills.

Job Description :

Candidate will be involved in verifying current and next generation SERDES products.

1. Writing constrained-random System Verilog test benches using UVM and VMM.
2. Writing new cover group and examine functional, assertions and code coverage.
3. Defining and tracking verification test plans.
4. Debugging RTL and gate-level simulations failures.

Location : Hyderabad, Telangana, India